MULTI-CORE STACK PROCESSOR ARCHITECTURE DESIGN BASED ON SHARED BUS INTERCONNECTION

With the development of the embedded system, single-core stack processor cannot meet the requirements of practical application in development cost, execution speed and power consumption. In order to improve the performance of stack processor and explore the value of multi-core stack processor, this paper adopted WISHBONE shared bus interconnect architecture. Through designing multi-core stack processor architecture, Forth system instructions, bus arbitration, and Universal Asynchronous Receiver/Transmitter (UART), a multi-core stack processor based on shared bus interconnection was initially constructed. The structure of the new processor was described by Verilog and VHDL language, the function was simulated by ISim tool, and the functionality was implemented on the field programmable gate array (FPGA) chip ultimately. The experimental results show that the design uses effective bus arbitration to achieve high computing performance with low hardware cost and power consumption, which lays a good foundation for further research and application of multi-core stack processor architecture.